1. Field of the Invention
The present invention relates to a plasma display panel and a method of driving the same. More specifically, the present invention relates to a plasma display panel having improved wall charge states due to driving waveforms of a reset period.
2. Discussion of the Related Art
Among flat panel displays, plasma display panels (PDPs) are being actively pursued due to their luminance, high luminous efficiency, and wide viewing angle.
The PDP displays text or images using plasma generated by a gas discharge, and it has hundreds of thousands to millions of pixels arranged in a matrix configuration.
A conventional PDP will now be described with reference to FIG. 1 and FIG. 2.
FIG. 1 is a partial perspective view of a conventional PDP.
Referring to FIG. 1, a plurality of pairs of electrodes, which include a scan electrode 4 and a sustain electrode 5, are arranged in parallel on a first substrate 1. The scan and sustain electrodes 4 and 5 are covered with a dielectric layer 2 and a protective layer 3. A plurality of address electrodes 8, covered with an insulating layer 7, is arranged on a second substrate 6. Barrier ribs 9 are formed on the insulating layer 7 in parallel with, and in between, the address electrodes 8. Phosphor layers 10 are formed on a surface of the insulating layer 7 and each side of the barrier ribs 9. The first substrate 1 and the second substrate 6 are sealed together with a discharge space 11 therebetween, so that the scan electrode 4 and the sustain electrode 5 pairs are perpendicular to the address electrodes 8. Portions of the discharge space 11 at intersections between the address electrodes 8 and the scan electrode 4 and the sustain electrode 5 pairs form discharge cells 12.
FIG. 2 is shows a typical electrode arrangement of the conventional PDP of FIG. 1.
Referring to FIG. 2, the PDP electrodes are arranged in an n×m matrix. The address electrodes A1 to Am are arranged in a column direction, and the scan electrodes Y1 to Yn and the sustain electrodes X1 to Xn are arranged in a zigzag configuration in a row direction. A discharge cell 12 of FIG. 2 corresponds to the discharge cell 12 of FIG. 1.
Referring to FIG. 3, a method of driving the conventional PDP will now be described. A gray scale is displayed by dividing a field into a plurality of subfields. In terms of a time period, one subfield includes a reset period PR, an address period PA, and a sustain period PS.
The reset period PR erases wall charges generated by a sustain discharge of a previous subfield and initializes a state of each discharge cell for a next addressing operation.
The address period PA selects addressed cells and accumulates wall charges in the addressed cells.
The sustain period PS performs a sustain discharge for displaying an image on the selected discharge cell. During the sustain period PS, sustain discharges are performed by alternately applying a sustain pulse to the sustain electrode X and the scan electrode Y.
Specifically, after the reset period PR, the wall charges should be in an optimum state so that stable addressing may take place in the following address period PA. This is particularly important when performing address discharges at a low voltage.
The reset period PR includes an erase section PR1, a rising ramp section PR2, and a falling ramp section PR3.
The erase section PR1 erases the charges generated during the sustain period PS of the previous subfield by the sustain discharge. The rising ramp section PR2 generates the wall charges in the scan electrodes Y, the sustain electrodes X and the address electrodes A. The falling ramp section PR3 erases some of the wall charges generated during the rising ramp period PR2 in order to more efficiently perform the address discharge.
During the rising ramp section PR2, a ramp voltage that gradually increases from a voltage Vs to a voltage Vset, which is a voltage higher than a discharge start voltage, is applied to the scan electrodes Y, while a voltage of 0 V is applied to the address electrodes A and the sustain electrodes X. While this ramp voltage is rising, a slight reset discharge occurs from the scan electrodes Y to the address electrodes A and the sustain electrodes X. This reset discharge simultaneously accumulates (−) wall charges in the scan electrodes Y and (+) wall charges in the address electrodes A and the sustain electrodes X.
During the falling ramp section PR3, a ramp voltage that decreases from a voltage Vs to a voltage Vn is applied to the scan electrodes Y, while the sustain electrodes X are maintained at a voltage Ve. While this ramp voltage is decreasing, a second slight reset discharge occurs in all discharge cells, which decreases (−) wall charges in the scan electrodes Y and (+) wall charges in the sustain electrodes X and the address electrodes A.
After the rising ramp voltage is applied to the scan electrodes Y during the rising ramp section PR2, if the PDP enters the falling ramp section PR3 without sufficiently observing a flat period of maintaining a voltage of Vs+Vset from a peak point of the ramp, the discharge required in the rising ramp section PR2 may not be performed sufficiently. Therefore, the desired state of the wall charges may not be formed sufficiently.
Also, during the falling ramp section PR3, if the PDP enters the address period PA without sufficiently observing a flat period of maintaining a voltage of Vn, the reset period PR may end before wall charges are uniformly formed within all discharge cells. Accordingly, the PDP may enter the address period PA without uniform wall charges, which may cause unreliable address discharges.